The present application relates to an interconnect structure having low line resistance and a method of forming the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structures typically include copper, Cu, since Cu based electrically conductive structures embedded in an interconnect dielectric material layer provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based electrically conductive structures.
As the Cu based electrically conductive structure feature sizes shrink, it is necessary to scale diffusion barrier thickness in order to minimize the volume of the Cu based electrically conductive structure and to enable low line and via resistance. Scaling sidewall diffusion barrier thickness allows maximization of Cu volume in interconnects and scaling the diffusion barrier thickness at the via bottom allows reduction of via resistance.
For void-free Cu fill at less than 24 nm critical dimension, an additional layer (i.e., a seed enhancement layer) is deposited to prevent diffusion barrier exposure during Cu plating, especially on the sidewalls. One example of a seed enhancement material is ruthenium (Ru). Without a seed enhancement layer, sidewall voids will form which can lead to poor electromigration (EM) performance of the interconnect structure.
Chemical mechanical polishing (CMP) of Cu based electrically conductive structures and Ru seed enhancement layers embedded in an interconnect dielectric material layer is challenging. Specifically, galvanic corrosion of Cu during Ru CMP results in Cu loss at the top interface. This Cu loss is a key contributor to high line resistance. There is thus a need to provide an interconnect structure that includes a seed enhancement layer, while eliminating Cu volume loss during CMP.